Micron sets 42 Gb/mm2 NAND density target for 2027

Micron plans to double its NAND flash storage density to 42 Gb/mm2 in the second half of 2027. The new G11 generation will also raise input/output speeds from 3,600 MT/s to 5,400 MT/s and reduce the energy required to transfer each bit by more than 25%.

The company outlined these specifications at an industry event this week. The density target represents a jump from the current G9 generation, which sits at approximately 21 Gb/mm2 in triple-level-cell form. Micron stated that these improvements aim to support high-capacity solid-state drives for client and data center applications, as well as storage devices built for artificial intelligence workloads.

A primary technical shift in the G11 design is the adoption of wafer-on-wafer bonding. This method allows the company to manufacture the memory array and the peripheral circuitry on separate wafers. Each wafer is then processed using a technology specific to its function before the two are joined. Micron has utilized CMOS-under-array designs for previous generations, but bonding provides greater flexibility to optimize the memory and logic components independently.

Scott DeBoer, Micron’s president and chief technology and products officer, confirmed the use of this bonding method. He stated that the company had previously promised to introduce the technology once it became cost-effective and relevant to product specifications. DeBoer described the timing as appropriate and labeled the G11 chips as the world’s most advanced NAND.

The G11 architecture will exceed 400 layers, although Micron has not disclosed the exact number of active wordlines. The company attributes the density gain to a combination of additional layers and a smaller memory cell pitch. This density figure exceeds the next-generation offerings from competitors Kioxia and Samsung. Micron intends to release further technical details in 2027, closer to the start of high-volume production.

Beyond the G11 generation, Micron indicated it will continue scaling in all three dimensions. The company is developing high-mobility materials and ultra-dense cell architectures to improve transistor characteristics and reduce internal energy consumption. DeBoer noted that both the industry and Micron are currently scaling by adding layers and shrinking cell dimensions.